MA-XA is a comprehensive and powerful assembler, which is capable of generating both relocatable and absolute object files. MA-XA includes a macro instruction processor and its syntax is fully compatible with MA-51 and ASM-51. The syntax is also compliant with the rules specified by Philips for address indirection and therefore allows both "@Ri" and "[Ri]".

To ease the migration of existing 8051 assembly code to the XA, RKitXA includes an 'instructions translator'.

This tool emits an *.AXA source file from an *.A51 source file by replacing 8051 instructions by their equivalent XA instructions.

New directives have been added to take account of the specific features of the XA such as code alignment.

Several different physical memory spaces can be addressed by using different types of instruction:

• The Code space contains machine code instructions and data constants. The full address range defined by the architecture is 16MB, but specific derivative parts may limit this to a lower figure. In addition parts usually have on-chip ROM so that single-chip implementations are possible for some applications. When all the code for the application can be contained in the on-chip ROM many of the pins on the package are dedicated to programmable input and output ‘ports’. However, in order to access external code space these ‘ports’ are lost and the pins serve as a multiplexed address and data bus. The Program counter has up to 24-bits and treats the code space as a linear array of memory.

• The Data space is partitioned in a similar manner to code space with the same upper limit of 16MB, but instead of perhaps 32KB of internal ROM there may be only 1KB of internal RAM. Also the data space is segmented with 256 segments each of 64KB. When data space is accessed special 8-bit segment registers provide the high part of an address while one of 8 16-bit registers often provides the low part of the address. This technique is particularly good for multi-tasking applications where the data for each task can be placed in different segments. In particular data memory may be accessed either directly, indirectly, indirectly with offset or indirectly with post increment.

• The architecture defines 16 16-bit ‘core’ registers, numbered from R0 to R15. The first derivative devices implement only R0 to R7, where R7 also serves as the Stack Pointer. In fact there are two independent stacks which are both referenced as R7 but one is available in ‘User’ mode while the other in restricted to ‘Supervisor’ mode. There is no 'Accumulator bottleneck’ as found in other architectures as registers R0 to R6 may be mixed freely in most instructions. Each half of registers R0 to R7 may be accessed as 8-bits e.g. R4H and R4L, and Registers R0 to R3 are 'banked' to provide compatibility with the 8051.

• The operating speed depends not only on the frequency of the clock but also the width of the external data bus ( 8 or 16 bits) and the number of wait states associated with each memory access. Internally the main data buses are all 16-bits wide and there are no wait-states. Consequently the XA is significantly faster when operating in single chip mode.

• An address space of 512 bytes is allocated to on-chip Special Function Registers (SFRs) that permit the control of Timers, Interrupt priorities and other peripherals. Generally, for any particular derivative only part of this address space is used. 512 bytes of off-chip SFRs is defined by the architecture and may be implemented in particular derivatives.