XSmart is an original concept that simplifies and speeds up your SoC prototyping and validation steps.

It is the best open and scalable development platform that can be used at any step of your development process:

• IP CPU validation,
• Peripheral design and validation,
• Customer demonstration,
• Software development and debugging.

These boards must be considered as a generic purpose development platform which integrates a lot of facilities:

• FPGA loading through the USB link.
• Communication with the FPGA through the USB link.
• FPGA bitstream protected with a 3DES key.
• Up to 311 IOs available on high speed connectors.
• Wide voltage range.
• Memorie access up to 100MHz.
• « Autoboot » mode: it can start up without any host.
• Software API to drive these boards.
• Raisonance IP blocks (ESDK) for code loading, complete emulation, trace, event, code coverage, protocol analysis available.
• Fully integrated in the Raisonance Integrated Debugger Environment (RIDE).
• Low cost.

The Xsmart board architecture is based on several components that allows the product scalability:

• A USB2,0 high speed link for the communication between the host and this platform.
• A wide XILINX® FPGA from the Spartan 3 to the Virtex V to implement your logic system.
• Several IOs to communicate with an other system or analog peripherals.
• Several SRAM memories connected independently on the FPGA.
• A FLASH memory to save the FPGA content for an auto boot mode.
• A small battery to save the 3DES key for using a FPGA bitstream encrypted to protect your IPs.

The most typical XSmart use is to implement in the main FPGA only the IP CPU and the Raisonance IP blocks. The peripherals are exported to an auxiliary board.

The full prototyped microcontroller consists of these two boards linked together as shown below:

XSmart exists in three different packages that can be easily integrated into your system:

• The first one, XSmart-M, is a plug with a SO-DIM PCB print as connector. Theses boards are a low cost solution and are based on a XILINX® Spartan® 3 FPGA.

• The second one, Xsmart-P, comes in a PCMCIA like package. It offers the opportunity to used a standard PCMCIA connector for the Ios interface and its metal package limits the digital noise on your system. These boards are based on the XILINX® Virtex® II FPGA and three deep memories.

• The last one, Xsmart-Q, comes as a daughter (piggy back) board with Samtec QTH connectors that allows high speed communication and offers more FPGA Ios. It also integrates a compact FLASH connector, LEDS, switch, BP, RS232 connected to the FPGA.

Xsmart ordering information schema:

Xsmart-S1000M

            |        | ->Q = QTH connectors; M = SO-DIM package; P = PCMCIA package
            |--------->S = Xilinx Spartan FPGA; V = Xilinx Virtex (II or IV) FPGA

Product	Connectors	FPGA	Nb IOs	Memories
XSmart-S400M	SO-DIM PCB print	XC3S400	80	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-S1000M	SO-DIM PCB print	XC3S1000	80	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-S1500M	SO-DIM PCB print	XC3S1500	80	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-S2000M	SO-DIM PCB print	XC3S2000	80	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-V500P	PCMCIA	XC2V500	54	3 x 512k x 16bit sync.
XSmart-V1000P	PCMCIA	XC2V1000	54	3 x 512k x 16bit sync.
XSmart-V1500P	PCMCIA	XC4V1500	54	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit sync.
XSmart-V2500P	PCMCIA	XC4V2500	54	1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit sync.
XSmart-V4000Q	Samtec QTH	XC4VLX40	193	1 x 512k x 36bit sync, 1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-V6000Q	Samtec QTH	XC4VLX60	193	1 x 512k x 36bit sync, 1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-V8000Q	Samtec QTH	XC4VLX80	311	1 x 512k x 36bit sync, 1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-V10000Q	Samtec QTH	XC4VLX100	311	1 x 512k x 36bit sync, 1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.
XSmart-V16000Q	Samtec QTH	XC4VLX160	311	1 x 512k x 36bit sync, 1 x 512k x 36bit sync pipelined, 2 x 256k x 36bit.

Facilities

Debug bus

The interface between Xsmart and the host is a USB2,0 link. This high speed serial interface, up to 480Mbit/s, allows you to load the FPGA bitstream but also to communicate with memories and FPGA registers through a FPGA bus that we call « Debug bus » that is a simple parallel interface.

API

Xsmart is delivered with a complete C Application Program Interface (API) with basic functions to read and write to the XSmart through the USB2.0 link. XSmart can be fully integrated in any system (protocol analyzer like ProxiSPY or JTAGSPY, emulator, or prototyping board).
The USB driver is completely managed by the XSmart API.

RIDE

Xsmart is fully integrated in RIDE (Raisonance Integrated Debugger Environnement) that allows you to load the application code, manage a high level emulator with ESDK (Emulator System Development kit) dedicated for the Xsmart and read the trace and debug the application.

Raisonance IP blocks

Some FPGA IP blocks have been developed specifically for the Xsmart platform. They allow you to avoid development timeon debugging features and to focus only on your design. These IP blocks, integral parts of ESDK, are dedicated for CPU instrumentation:

• XTrace: Records and stores everything that you want/need: CPU access, peripherals events, internal signals, ...

• XEmu: Allows the application debugging and to easily create your own emulator: step by step, breakpoints, data watches, ...

• XEvent: Generates specific event to start the trace, set a breakpoint on a specific event: memory access, pattern matching, simple bit event, ...

• XCodCov: Performs a code or data coverage for application profilling.

Some other IP blocks exist dedicated for the protocol analysis (JTAG, I2C, ISO7816, ISO14443, ...). Don't hesitate to ask us for more information.

Success stories

Raisonance has developed ESDK examples based on freeware IPs: T51 (8 bit) and miniMips (32 bits), Xsmart is used as a generic emulator for the 8051 and 80251 IP cores from Dolphin Integration. It is also used to prototype a RISC 16 bt core and its peripherals (Inside Contactless microcontroller: MicroPass). Electronic Marin uses the XSmart board to design their own smart card emulator. ProxiLAB and ProxiSPY, smart card laboratory tools, integrate an Xsmart board for the product management and the protocol analysis.