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Main Features
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Fully transparent operation up to 44 MHz
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Full support for embedded ROM versions
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Code banking for applications up to 512 K
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Source level debugging with full 'C' variable support
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Unlimited number of hardware breakpoints on all addressable
spaces, even in banking mode
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Multi-mode real- time trace
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Highly advanced design using multiple FPGAs and SMD technology
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Supports nearly all 8051 derivatives (both internal and external
ROM versions), and Dallas DS320
Supported chips
The emulator is connected to a pod via a 0.2 m ribbon cable.
This pod contains the emulation chip and plugs into the target
system either directly or through an adapter-probe assembly. Each
pod supports a sub-family of devices.
To change from one microcontroller to another within a sub-family,
it is only necessary to replace the adapter-probe assembly, or
the emulation chip. Look at the available pods
and the supported microcontrollers.
System specification
* Transparency
The PCE-5140C does not intrude or interfere with the microcontroller's
interrupts, serial port, stack or code space.
* Memory mapping
- One byte resolution over the full address range (both XDATA
and CODE)
- Code can be up-loaded from the target board's firmware (EPROM)
- Access is provided to the external RAM (read or write) during
program execution
* Emulation space memory
128 Kbytes code (bank switching) upgradeable to 512 Kbytes
64 Kbytes XDATA
* Emulation clock
Clock source:
- Pod oscillator
- Target board crystal
- Target board oscillator
The pods are supplied with a socketed 12 MHz oscillator which
may be changed by the user.
* Execution modes
- Continuous, with breakpoints
- Single stepping
- Line stepping (for high-level source debugging)
- Step over calls or interrupts
* External synchronization
A TTL output signal indicates execution within a user-defined
block of code.
* Breakpoints
- Program breakpoints on the whole code space (up to 512 Kbytes)
- 64 Kbytes read / write / access breakpoints in external RAM
- Break on direct access to internal bit or byte memory (read
/ write / access)
* Target board reset
A validation flag allows a "hardware" reset on the target
board to be either accepted or ignored by the emulator.
* Internal timer
The PCE-5140C supports a 32 bit-timer, which is used for execution
control and trace features. Time can be displayed in to 2 different
modes: CPU cycles or "hourly format" (hh:mm:ssss).
* Probes
The PCE-5140C is supplied with 2 user probes, for recording up
to 16 external signals. Each probe has test clips and a ground
connector. It can optionally be supplied with 2 additional probes
for monitoring a further 16 external signals.
* Display
- LED to indicate the status of each trace input
- Trace display is in disassembled symbolic, binary/hex form,
or high-level source code and can be saved to a file
- Graphic display
- Trace display during program execution
* Frames
8000 frames by 64 bits (extendible to 80 bits):
- PC + time + 16 external signals
- PC + time + 8 external signals + 1 XDATA variable
* Modes
The PCE-51 offers a wide range of trace modes, designed to make
optimum use of the trigger conditions and the capacity of the
trace buffer.
- Simple mode: recording of pre-filtered instructions, using trace
control flags
- Continuous mode: recording of instruction blocks
- Synchronous mode: for slow processes, samples can be taken every
N clocks, where N is specified by the user
- 'One Shot' mode
Bank switching
- Emulation up to 128 K of code, upgradable to 512 K.
- Hardware breakpoints and trace flags can be placed anywhere
within the 512 K code space.
- The extra address signals, used to define the active bank, are
read from the target board, through a trace probe.
- As in the "standard" mode, it is not necessary to
fit an EPROM to the target board. The entire code space can be
mapped with a resolution of 1 byte as either emulation RAM or
as the target system.
- It is possible to move to any point, in any bank of the code
space, simply by specifying the symbolic address.
Integrated Development Environment
The PCE-5140C is fully managed by the Integrated Development
Environment RIDE.
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